Integrated Circuit devices such as DRAM (Dynamic Random Access Memory) and Flash (electrically erasable/programmable non-volatile memory) typically require for operation a number of voltages for separate operations including storing, reading, and erasing data. These voltages are internally generated by using an externally supplied voltage source often referred to as Vdd.
A conventional DRAM device may have a Vpp supply for providing a high voltage for driving a wordline above the Vdd level stored in a memory cell, a Vdd/2 supply for driving the cell plate to a mid-rail potential, and a Vbb supply for providing a negative back bias potential to the memory cell substrate.
A conventional NAND Flash device may have pump circuits for generating Vpass for application to unselected wordlines in a selected block during page read operations, Vpgm for applying to selected wordlines in page program operations, and Vers for applying to wordlines in a selected block during block erase operations.
These internal voltage supply circuits occupy significant chip area and increase the die size and cost, this is particularly the case if capacitive pump circuits are used which require large pump and reservoir capacitors. The voltage supply circuits may also limit performance. For example, in a NAND Flash device the Vpgm voltage must be pulsed and applied repeatedly to a wordline in alternation with verify read operations. The time that it takes to charge the wordline adds overhead to each program/verify read cycle and can extend the program time parameter tPROG which is a critical factor in NAND Flash performance.
In some integrated circuit devices, for example LPDDR2 (Low-Power Double Data Rate 2) DRAM as described in JEDEC (Joint Electron Device Engineering Council) specification JESD209-2B, the number of banks that can be activated within a given time window depends of tFAW (Four bank Activate Window) which is specified as 50 ns for the higher speed grades. Although commands to activate all 8 banks could be issued to the device within this period of time, the tFAW restriction limits the current drive requirements on the internal Vpp generator, and perhaps other internal voltage generators as well, by forcing the user to activate a maximum of four banks in the rolling tFAW window. This restriction allows a size of the Vpp generator to be reduced from that required for unrestricted bank activation, thereby saving die area and cost.
When a number of memory devices are combined to provide a larger memory subsystem, they are often connected to a common shared bus. In this case there may not be sufficient command bandwidth to exercise all devices to their maximum capabilities. For example, in the case of eight LPDDR2 DRAM devices connected to a shared command bus operating at 400 MHz, it is impossible to issue four bank activate commands to each device within a 50 ns tFAW window. One command requires two edges of the clock or 2.5 ns. Therefore at least some of the devices will not be fully utilizing the capabilities of their internal Vpp generators. It is not practical for DRAM manufacturers to offer different variants of memory products with a range of internal voltage generator drive capabilities and optimized die size. Memory product manufacturers rely on high volume of standardized product to drive costs down.